Rivos

An intern position focused on developing the design flows for the silicon interposer, from

netlist to GDS including but not limited to prototyping, unit cell creation, bump

management, place and route, electrical extraction and analysis, DRC, and LVS.

Responsibilities

• As a Silicon Interposer Design Flow Development intern, you will own or participate in the following: 
• Create unit cells used in the Si interposer.
• Develop scripts to automate the signal/shielding routings on interposer.
• Develop flows to extract electrical models for SI and PI analysis.
• Develop flows to perform DRC and LVS for the interposer.
• Develop 3DIC design flows based on the 3Dblox language.
• Interface with EDA vendors to solve issues, evaluate tools and improve the flow.
• Work with silicon manufacturers to understand design rules and implement verification tools.

Requirements

• Strong technical background in VLSI, ASIC and EDA fundamentals.
• Experiences with EDA tools such as Innovus, Virtuoso, Calibre/Pegasus, Quantus, Voltus etc.
• Strong scripting skills in multiple languages (Shell and Tcl, Python).
• Basic understanding of silicon interposer technology.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, highly self-motivated and self-starter with minimum supervision.
• Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

• Current student for PhD or Master’s Degree.