NXP

Responsibilities

• Develop RTL for digital IPs or subsystems based on architectural requirements
• Develop functional timing constraints for IPs
• Run IP check flows of Lint, CDC/RDC, DFT, Synthesis, etc.
• Write IP documents like block guide, integration guide, creation guide

Requirements

• 3+ years of work experience in RTL Design and Verification
• Master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines
• Mandatory Tool Exposure: NCSim/VCS, Spyglass or Questa LINT/CDC
• Mandatory Skills: Verilog/SystemVerilog
• Nice to have USB or multimedia(display, graphic, video) knowledge.

More information about NXP in Greater China...