STMicroelectronics

OUR STORY

At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips forms the hidden part of the world we live in today.

When you join ST, you will be part of a global business of more than 115+ nationalities and present in 40 countries, 50,000+, diverse and dedicated creators & makers of technology around the world!

Developing technologies takes more than talent: it takes amazing people who understands collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential.

Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future!

YOUR ROLE

ST R&D supports leading edge system companies with broadrange applications by providing complete design platforms and production capabilities for high end SoC / ASIC using the most advanced technologies nodes. In this complex context, ST is looking for new talents starting from students in electronic engineering willing to engage in a master-degree thesis.

Thesis subject: SRAM ECC (Error-Correction-Code) Intellectual Property validation through FPGA

Outline of the thesis activities:

• Learning phase
  • HW/SW environment, main tools and R&D packages
  • IP architecture and design specification
  • FPGA integration, synthesis and compilation, dedicated SW/platform
• Core
  • HW and SW architecture definition
  • HW design, including FPGA programming for IP emulation
  • HW and SW debug and verification
  • Stress test through particles strike
• Wrap-up and conclusions
  • Results consolidation
  • Thesis and documents preparation
  • R&D internal knowledge sharing

Duration of the activities: 8 - 10 months

YOUR SKILLS & EXPERIENCES

• Candidates with bachelor’s and close to complete master’s degree in electronic engineering
• Digital design flow, Single/Dual port SRAM basic knowledge
• Verilog, SystemVerilog knowledge
• C/C++ and Python knowledge
• Unix/ Linux OS knowledge
• English spoken/ written is a must

Location: On-site in Castelletto design center (Cornaredo, Milan west-side) and smart-working.

We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, Equity and Inclusion (DEI) is part of our company culture. Our DEI vision is, “At ST, you can be the true version of yourself”, we value all employee contributions and have zero tolerance for any kind of discrimination.

Joining us is also about a greater work-life balance and workplace with equal opportunities. Dedicated Employee Resource Groups for women and LGBTQIA+, hybrid work arrangements are amongst the many DEI & Sustainability initiatives that make us a great place to evolve your career.

To discover more, visit st.com/careers