About the team: This team is at the forefront of technological innovation, specializing in the design, development, and production of CPUs for our data center servers. Leveraging a team of highly skilled engineers, researchers, and experts, the unit focuses on creating high-performance, energy-efficient, and reliable chips that power a wide range of electronic devices and systems. Responsibilities - You will be responsible for specifying and/or micro-architecting/implementation of digital blocks in advanced mixed-signal circuits with embedded micro-controller, advanced DFT architectures and very low power design requirements. - You will be responsible for various front end methodology flows that include pre-silicon power analysis, clock domain crossing, reset domain crossing and unified power flow UPF). - You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Minimum Qualifications: - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals (control and data path). - Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers, reset domain crossing, unified power flow, logic equivalence checkers). - Working knowledge of synthesis, static timing, and DFT (scan, analog/digital functional/production test). - Good SERDES and high speed clock architecture knowledge - Strong communication and presentation skills. Preferred Qualifications: - BS Degree with 5 years of experience, or Masters degree or PhD with 3 years of experience - Major in either Electrical or Computer Engineering, or STEM related field - Deep knowledge of Algorithm developments. - UCIe, PCIe, DDR, UAlink knowledge is a plus - ADC based SERDES knowledge is a plus - Being familiar with link analysis and modeling is a plus
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