Seagate Technology

About our group:

The group is part of Seagate’s VLSI Organization spread globally across multiple sites. Seagate designs world class controller SoCs for their HDDs. The group is responsible for the development of full custom ASICs for leading edge storage solutions.

About the role - you will:

• Work closely in the Design Implementation team for physical design, physical verification & power related activities across various SoCs
• Own complete Physical Design & Physical Verification flow for multiple blocks
• Work on Floor planning, power planning, P&R, CTS, timing closure, IR analysis, and formal equivalence for block level, full chip hierarchical, and flat designs
• Own parasitic extraction, timing closure, signal integrity, and timing ECO generation/ implementation
• Work on creating setup and scripts for DRC, LVS, Antenna, and density checks, report generation, analysis, debug, and implementing the fixes in the physical design database
• Own complete IR/IVD & ESD analysis flow for multiple blocks and chip level
• Work on Power mesh creation at various IPs (analog, digital Hardmacs, pad-ring) and full chip level
• Work closely with full chip physical design activities like bumping and RDL routing
• Interface with full chip level engineers for chip finishing tasks such as LVS, DRC, Antenna check, etc.

About you:

• Self-starter and self-motivated personality
• Ability to work with ASIC teams and other integration team members
• Capable of working with general instructions on routine work and detailed instruction on new projects
• Shares knowledge with others and is keen to build expertise by working collaboratively with team members
• Ability and willingness to work in a multi-cultural environment and across multiple timezones

Your experience includes:

• Experience/exposure to high-speed digital physical design and physical verification including ASIC through semi-custom high-speed digital designs from PD through tape out
• Hands-on experience on physical design / verification flow (floor planning, power planning, P&R, CTS, Timing closure, DRC, LVS). Exposure to EM, IR, low power design with UPF
• Technology node: 7nm/ 12nm/ 16nm/ 28nm
• Strong scripting skills using Tcl, PERL, and Make based flow
• Strong problem solving and debugging skills
• Good team player with strong verbal and written communication skills

Location:

Our site in Pune is dynamic, both in our cutting-edge, innovative work, as well as our vibrant on-site food, and athletic and personal development opportunities for our 400+ employees. You can enjoy breakfast, lunch, or dinner from one of four cafeterias in the park. Take a break from your workday and participate in one of our many walkathons or compete against your colleagues in carrom, chess and table tennis. Learn about a technical topic outside your area of expertise at one of our monthly Technical Speaker Series, or attend one of the frequent on-site cultural festivals, celebrations, and community volunteer opportunities. 

Location: Pune, India

Travel: None