Posted: Nov 14, 2023
Role Number:200519284
As an ASIC Design Engineer, the individual’s primary responsibility will be RTL design. This will include block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs
Key Qualifications
Description
Work with systems team to understand the top level requirements of the digital functions and develop detailed specifications Implement the function in Verilog RTL to specification Perform unit level testing on the RTL function Support the DV team by writing self-checking tests as required Supporting all design integration activities like Lint, CDC, Synthesis & ECO Working with Physical Design Team on STA, physical, power and logical issues
Education & Experience
BS degree in technical discipline with minimum 3 years of relevant experience.
Additional Requirements
Pay & Benefits