Apple

Summary

Posted: Jun 27, 2025

Weekly Hours: 40

Role Number:200609431

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and designing goals. Work on timing, physical and electrical verification. Drive the signoff closure for the partitions. Resolve design and flowing issues related to physical design, identify potential solutions and drive execution. Design and manufacture processor and system-on-chip (SoC) for Apple. Implement complete chip design from netlist to tape-out. Perform floorplanning, placement, clocking and routing for the design while ensuring best PPA. Drive best in class Physical Design construction and optimization recipes for performance, power and area (PPA). Collaborate to drive methodologies and best know methods to streamline PD work, create guidelines and checklists, drive execution and track progress. Consider various tradeoffs to optimize for high frequency and power sensitive designs while achieving smallest area. Oversee and resolve design and flow issues related to physical design. Ensure design closure across analysis disciplines including STA, Physical verification, Electrical analysis, Functional verification. Work with various top level teams and provide and implement feedback for smooth integration. Identify potential solutions and driving execution. Work closely with the FE design team to understand chip architecture and drive physical aspects early in design cycle. Provide feedback to FE team for synthesis recipe updates as well as suggest design changes to work best for PD. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master's degree or foreign equivalent in Electric Engineering, Computer Engineering, Computer Science or related field.
• Experience and/or education must include:
• Digital Circuit Design – Understanding the functionality of the designs
• Semiconductor Device Physics – Knowledge about the MOSFET/FINFET to help decide on the area/power tradeoff
• Scripting in Perl or Tcl – To Automate and improve the efficiency for the PnR implementation work
• Floorplanning – Ensure optimal macro placement and pin placement for the design
• Placement and routing optimization – optimize logic placement and routing for best area, power, performance, including custom placement and routing
• Clock tree synthesis – understand and implement best clocking for the design
• Static Timing Analysis – analyze and ensure design closure for STA
• Physical Design Verification – Layout updates to ensure design meets DRC/ LVS requirements
• Electrical analysis – Understanding of PG grid, IR, Electromigration
• Analysis and Debug – Thorough analysis skills to understand, debug and resolve issues in flow or methodology

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.