Lead Engineer - Design to Silicon Correlation
NVIDIA - Santa Clara, CAIC Package Design Engineer
Apple - Santa Clara, CASilicon Photonics Design & Packaging Engineer
Apple - Santa Clara, CAASIC Design Engineer - Pixel IP
Apple - Cupertino, CASoC Physical Design Engineer, STA/Timing
Apple - Sunnyvale, CAGPU Design Engineer – Memory Hierarchy
Apple - Santa Clara, CASoC Physical Design Engineer, STA/Timing
Apple - Beaverton, ORDC-DC Power System Design Engineer
Apple - Austin, TXPrincipal Hardware Design Engineer
PsiQuantum - Palo Alto, CASenior ASIC Physical Design and Timing Engineer
NVIDIA - Santa Clara, CA