Job Description:
- Chip/Block level floorplan,
- Clock tree synthesis,
- Place & Route,
- RC extraction,
- STA, timing closure,
- IR/EM analysis and fix,
- DRC/LVS/ERC analysis and fix,
- Tape-out sign off.
- APR Flow development
Qualifications:
- BCH degree and above in EE/CS.
- Experienced in digital design/design flow/APR chip implementation related field.
- Experienced in advanced process nodes (28nm and below)
- Familiar with Script languages (shell, python, TCL) or C/C++
- Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology.
- Good customer-oriented attitude and communication skills.
- Good command of Japanese.
- Highly welcome candidates who have less experience but have good related design experience, working attitude and are self-motivated.
- English is a plus.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Read Full Description