As CAD engineer, Support and enhance Analog CAD flow in all aspects of the design cycle, which includes front end simulation, back-end layout, verification, and tape-out
Work with PDKs in ADE from multiple foundries and be able to integrate different methodologies into a cohesive common format for product developers
Support ClioSoft revision control methodologies and databases
Support license management and monitoring
Support combining schematic/netlist, VerilogAMS & parasitic extracted view of cells for chip level mixed-signal simulation
Requirements:
BSEE and 5+ years of relevant experience working on Cadence Virtuoso CAD development and working on all aspects of the product development flow
Demonstrated experience in the use of skill code to enhance ADE environments
Use of Python, Perl, and other scripting languages to enhance automation a strong plus
Experience working with different pdks form different foundries and understanding how to setup and enhance
Business level Japanese & English communication skill