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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 3 years of experience in physical design.
- Experience in high-performance, low-power physical design and implementation techniques with industry standard synthesis and PnR tools.
- Experience in one or more sign-off convergence within the STA electrical checks and physical verification domains.
Preferred qualifications:
- 3 years of industry experience with high-performance CPUs.
- Fundamental knowledge of computer architecture, logic design (RTL), and Verilog/SystemVerilog.
- Working knowledge of CPUs including critical iterations for timing and low-power micro-architecture and implementation techniques for CPUs.
- Proficiency in using Static Timing Analysis, power grid network delivery, and power analysis tools.
About the Job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Develop RTL2GDS Physical Design tools and flows for advanced CPU designs to achieve Performance, Power, Area (PPA).
- Collaborate with the RTL Design teams on micro-architectural critical items for timing and power convergence.
- Manage block and hierarchical design physical implementation and Quality of Result (QoR) (e.g., power, timing, area).
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