Job Details:

Job Description: 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

About the Business Group: NEX is the next growth engine for Intel. Intel NEX chips and platforms securely handle data in Wireless networks to bring high performance computing to the Edge. We create standard products and custom silicon for our customers, enabling them to win deployments with major telecom customers. NEX has its own dedicated engineering group, and this job is positioned to support IP development (both internal and 3rd party), as well as broad front-end (RTL/verification) tools and flow support for multiple concurrent NEX projects.

This Verification, Design, and TFM Engineer is required to conceptualize, implement, and deploy best in class Front End tools, flows and methodology while designing IP and subsystems for SOC projects. Work closely with logic design and verification teams, understand requirements and challenges, find solutions and help them set the flow and tools with automation. Candidate will be responsible for developing and supporting Front End EDA tools services to ensure efficient design activities and will be interfacing with internal (Intel specific tools and flows) as well as industry/vendor experts (synopsys/cadence/mentor and others as may). The position will entail the employee to actively participate with Design Engineers, Design automation engineers on active debugging, root causing, and troubleshooting - in addition to identifying and pursuing design productivity improvements.

Responsibilities include but not limited to:

• Driving the overall FE Tools flows and methodology enablement for Network and Edge products, interfacing with Intel CAD teams and flow experts and EDA vendors.
• Develop, Evaluate and Deploy required tools, develop methodology using automation and tool development techniques and BKMs, including anticipating/understanding future project teams needs and requirements. You will be expected to resolve designer's and verifiers tool/methodology issues on path to Tape Outs.
• Learn and explore new AI ML tools and solutions to help designer and verifier improve overall design cycle efficiency
• Providing support for design ramp up to execution through training/documentation/presentation,
• You will require to be involved in interacting with EDA providers and ensuring required tools features available for the projects with high quality.

The Verification, Design, and TFM Engineer should have the following behavioral traits:

• Demonstrated adaptability: ability to move smoothly between EDA platforms, drive temporary workarounds as well as permanent solutions, and switch context day-to-day between multiple projects.
• Strong communication skills: this position will interact across multiple project teams, external EDA vendor interaction, and internal EDA partners.

Qualifications:

Minimum qualifications:

• BS in Electrical Engineering, Computer Engineering, Computer Science or related field with 6+ years of experience.
• 5+ years of experience with Verilog, System Verilog, RTL Design, Simulation, UVM and static checks, Clock and Reset Domain Crossing, and / or other pre-silicon quality and validation tools.
• 3+ years of experience with native usage experience with state of the art industry front-end EDA tools such as Synopsys/Cadence/Mentor
• 3+ years of experience designing IP and subsystems for integration into SOC or ASIC projects.
• 3+ years of experience with development of verification test benches and environments, at IP/partition or higher level hierarchy .

Preferred Qualifications:

• BS in computer science or computer engineering or related field with 9+ years of experience
• IP and subsystem design or verification experience with 3rd party IP such as ARM, Cadence, or Synopsys.
• Experience customizing and managing design flow and methodologies with scripts and routines in a Linux environment and direct experience in TFM
• Demonstrated team leadership including documentation, reusability of work, training, mentorship, and cross-functional work.
• Experience with AI/ML techniques for improving verification performance, runtime, and/or compute efficiency.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Texas, Austin

Additional Locations:

Business group:

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.