Job Details:

Job Description: 

At Intel, we work every single day to design and manufacture silicon products as the fundamental building blocks that empower people's digital lives. Do you love contributing to flagship products in cutting edge process nodes? Do you love solving technical challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver solutions for products that impact customers' lives?

Intel's Design Methodology Enablement (DME) team is looking for an experienced senior physical design engineer to help define tools, flows, and methodologies (TFM) for development of Intel's flagship Networking and Edge products.

As a Senior Physical Design Engineer, you will play an integral role in contributing to the development, deployment, and support of the physical design environment used across multiple SoCs. The candidate is expected to develop and support solutions in a wide variety of activities related to synthesis (Fusion Compiler), hard macro integration, placement, CTS, route, timing correlation, and overall physical convergence. Candidate is also expected to participate in the development of next generation of TFM and work closely with both external and internal vendors.

You will be responsible for, but not limited to: 

• Participate and lead others in developing TFM automation and enhancements.
• Contributions towards the physical design system and physical implementation (floorplanning, power grid insertion, placement, CTS, route).
• Troubleshoot a wide variety of physical design complex issues and apply proactive intervention.
• Opportunity to work closely with RTL teams, SD teams, and EDA tool vendors.

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CADbased automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and thirdparty vendor teams to continuously improve physical design methodologies and efficiencies.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

MINIMUM REQUIREMENTS

• Master's degree in electrical or computer engineering with 10+ years of industry experience or bachelor's degree with 13+ years of industry experience.
• Expert in physical design methodologies and sub-micron technology Place and Route (Fusion Compiler).
• Tcl/Perl/Python coding skills to automate design process and improve efficiency in EDA tool suites.
• Highly experienced in static timing analysis (PrimeTime).
• Strong verbal and written communication skills in English.
• Excellent teamwork skills including ability to work with multiple and remote groups worldwide.
• Motivated self-starter, with strong ability to work independently as well as in a team environment.
• Flexibility and maturity in facing uncertainties and changing priorities/responsibilities.
• Act with velocity and a strong sense of urgency.
• Respect cultural diversity and sensitivity.
• Agility in learning, improving, and innovating.

DESIRED REQUIREMENTS

• Experience with physical verification (DRC/LVS/Antenna), EM/IR-Drop/Xtalk analysis (PT-SI), and formal verification (Formality or LEC).

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

Experienced Hire

Shift:

Shift 1 (Costa Rica)

Primary Location: 

Costa Rica, San Jose

Additional Locations:

Business group:

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.