Microsoft

The Microsoft Silicon Engineering and Solutions Team is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas like RTL & VIP Design, Design Verification, Validation, Simulation/Debug, Coverage and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our Design/Verification engineers so that they can deliver cutting-edge silicon solutions for Microsoft. 

For all CAD roles, you will:   

• Be part of a central FE CAD team that drives common FE methodologies for SoC and IP design.  
• Be the expert in your domain and act in partnership with the execution team.  
• Provide leadership to the design community for the CAD domain for which you are responsible.  
• Work with stakeholders across the Microsoft Silicon group to collect TFM requirements.  
• Develop, enhance, and integrate common design and verification IP for organization-wide use.   
• Work with EDA vendors to adopt the most optimal solutions for silicon verification and design.  
• Mentor junior team members and summer interns.  

Required:   

• BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.   
• 7+ years of experience in digital design or CAD flows/tools development in this area.   
• Well-rounded and familiar with most Front-End Tools, Flows and Methodologies.   
• Experience working on SV/UVM verification methodology and maintaining VIP components.
• Experience with Logic Design compilation, elaboration and simulation 
• Experienced writing scripts/software with industry standard languages like Python, TCL, Perl, C/C++ or Java (Python preferred)  
• Experience using industry standard HDLs like SystemVerilog/Verilog.   
• Expertise in one of the following areas: 
• Design compile, elaboration and filelist/libraries handling. 
• Design release packaging and qualification, Functional coverage, test planning 
• SoC integration.

Additional Preferred:   

• MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience.  
• 7+ years of relevant experience.  
• Strong Object-Oriented Programming expertise.  
• Expertise in Computer Architecture, as well as CPU/SoC design principles.   
• Expertise in UVM/SV Verification methodologies, VIP components 
• Exposure to Test planning tools, Coverage dump, merging, Triage and debug technologies 
• Exposure to Portable stimulus methodology. 
• Hands on experience working on VCS/Xcelium, VManager, Formal verification, 3PIP VIPs. 
• Expertise driving Simulation Technology and methodology for efficient Design Verification. 

#SCHIEINDIA

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.