Cadence Design Systems

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position: Lead Design Engineer

Location: Nanjing

Work scope:

Responsible for the Highspeed Serdes and DDR IP EVB board schematic and PCB design;

Responsible for PCIE, USB, 10G-KR Serdes IP characterization testing;

Responsible for DDR4/LPDDR4X/DDR5/LPDDR5 IP characterization testing;

Generate auto testing code for the characterization test plan;

Co-work with RD for the IP issue debug;

Required Qualifications:

1. BS/MS in Electrical/Computer Engineering (or similar degree), with 3+ years relevant industry experience

2. Good basic knowledge of digital and analog circuits

3.Have experience of the hardware design

4. Familiar with Oscilloscope,BERT, VNC

5. Familiar with Python or C

6. Good communication skills in Chinese and English, team-work ability

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