AMD

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Silicon Design Verification Engineer

The role:

A Design Verification Engineering role in our Security IP (SECIP) team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

The person:

A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

• Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
• Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
• Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
• Participate in subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
• Debug and solve integration issues with SoC Integration and SoC DV teams
• Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members

Preferred experience:

• BSc with a minimum of 5 years of relevant experience; or MSc with a minimum of 3 years; or PhD in a directly related research area and a minimum of 1 year
• Proven understanding of MP subsystem architecture, FPGA based simulation techniques or emulation methodology
• Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
• Excellent knowledge about state-of-art verification methodology and best practices, UVM, C-DPI, and FPV
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
• Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

Academic credentials:

• Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
• Master's Degree preferred

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.