Synopsys

Requisition Number

48459BR

Job Description and Requirements

You will be part of the R&D in Solutions Group at our Munich Design Center, Germany. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design using latest HDL and design Flows.

Responsibilities

• Will be working on IP design for the next generation High Performance Ethernet protocols for commercial, Enterprise and Automotive applications
• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
• Be an individual contributor in the Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
• May need to interact with customers to discuss/ understand customers’ specification requirements, if needed .
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Key Qualifications & Experience

Typically requires a BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

• Knowledge of one or more of protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro/ SD-MMC/ /USB/AMBA (AMBA2, AXI). Prior Ethernet knowledge will be a definite plus.
• Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools
• Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background.
• Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus.
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.
• In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative.

Solutions Group

The Solutions Group provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate timeto-market.

About Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Hiring Location

GERMANY - Munich

Hire Type

Employee

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Country

Germany

Business Title (Title for Job Posting)

ASIC Digital Design, Staff Engineer