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The Teradyne Hardware Engineering team is looking for a highly-motivated, energetic, technically driven Semiconductor Engineer to focus on digital FPGA design verification for products within the Semiconductor Test division. Development occurs in a dynamic and challenging multi-site development environment. This individual will report directly to the Hardware Engineering Manager.
Do functional verification cycle of Next Generation Automatic Test Equipment (ATE) instrument design verification projects by performing the following duties:
1. Develop verification plan/strategy to cover different verification aspects:
2. Develop test environment and test coverage using Constrained Random in System Verilog and UVM/Assertion-Based methodology.
Have 2+ years of work experience in the following:
⦁ Proprietary interfaces (IP) and simulation tools.
⦁ Digital design verification.
⦁ Block, sub system and system level verification concepts
⦁ Some IP Protocol knowledge (e.g SPI, AXI, and DDR)
⦁ Universal Verification Methodology (UVM) based coverage driven verification methodology.
⦁ System Verilog Assertion-Based methodology.
⦁ Good at Object Oriented Programming (OOP) and code-reuse
⦁ Bachelor’s degree in Engineering (Electronics, Electrical Engineering, or related field).
⦁ 2+ years of experience in digital design verification.
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