Cisco

Job Description

职位描述：

We are looking for Hardware Engineer Intern to join Enterprise Switching HW team in Cisco CRDC (China R&D Center)， Shanghai. You will have the opportunity to work with the talents in Cisco engineering to develop the Enterprise Switching Hardware with cutting edge technology and methodologies.

我们正在寻找硬件实习工程师加入我们思科CRDC的企业网交换机硬件上海团队。您将有机会与思科工程团队的人才合作，参与企业网交换产品的硬件开发。

Cisco's Enterprise Switching products - Catalyst 9000 switches are the next generation in the legendary Catalyst family of enterprise LAN access, distribution and core switches. Catalyst 9000 family of switches has been designed as the foundation for an entirely new era of networking to meet the ever- changing needs of the enterprise network, today and well into the future. Our HW team focus on one of enterprise switching HW platform.

思科的企业交换产品--Catalyst 9000交换机是传奇的Catalyst系列交换机的下一代产品， 提供企业网以太网接入，分配和核心交换。 Catalyst 9000系列交换机为新一代网络而设计，可满足当今和未来企业网络不断变化的需求。我们的硬件团队负责其中一个系列的企业网交换硬件平台的开发。

Responsibilities:

工作职责：

• Participate in the real hardware development process, the job may include one or some of the listed items: HW spec, schematic design, Logical design, SI measurement, HW function verification test, test environment setup and test script developing etc.
• Co-Work with ECAD, Mech, SI, Power, diagnostics and SW closely for the development
• Assist in HW Lab test facility set-up and maintenance。
• 参与企业交换机的硬件开发过程，工作包括以下所列一项或多项任务：硬件文档设计，电路原理图设计，逻辑设计，信号完整性测试，原型板功能性验证, 以及硬件测试环境搭建和测试脚本编写等等。
• 在开发过程中和其他开发团队(ECAD，机械，信号完整性，电源，诊断测试和软件团队)紧密合作开发
• 协助硬件实验室的测试环境搭建和维护。

Requirements:

技能要求：

• Solid technical knowledge on digital/analog circuit design， familiar with the basic board development tools and process
• Familiar with Xilinx or Altera logic devices and the relevant logical design tools/process
• Fundamental Signal integrity knowledge and understand the high-speed digital design
• Familiar with script coding is a plus.
• Proactive and willing to take challenges.
• Teamwork and strong communication skills are essential.
• Excellent written and verbal English skills.
• 扎实的数字电路和模拟电路理论基础，了解基本的电路板开发工具和流程。
• 接触过Xilinx或Altera的逻辑器件，了解及其设计方法和流程。
• 熟悉信号完整性基础知识，对高速数字电路的设计有基本了解。
• 熟悉脚本编程为佳
• 积极主动，愿意接受挑战。
• 良好的沟通能力和团队合作精神。
• 优秀的英语书面和口头沟通技能。

Working Time Requirements:

工作时间要求：

• At least 3 working days (from Monday to Friday) per week
• 9:00am-18:00pm per day
• 每周最少3个工作日（星期一至星期五）
• 每天9:00至18:00

Educational Background：

学历：

EE, Computer Science, Communication, Automation or relevant Major preferred

电子，计算机，通讯，自控或相关专业

Location：

工作地点：

Shanghai, Caohejing

上海，漕河泾