ByteDance

Responsibilities

Team Introduction

Our team is building industry leading, highly efficient and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec algorithm modeling engineers to design algorithms and C-model for advanced video encoding and processing implemented in dedicated hardware accelerators. The successful candidate will be part of a fast growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

Responsibilities:

• Design and develop algorithms and C/C++ models for advanced video encoding and processing for hardware implementation
• Support use of C/C++ models for architectural modeling and algorithm benchmarking
• Collaborate with the HW architecture and design team for optimal algorithm and architecture co-design

Qualifications

Minimum Qualifications

• BS degree or above in Electrical/Computer Engineering, Computer Science, or equivalent fields
• Strong knowledge in video coding standards (AVC/H.264, HEVC/H.265, AV1, and VVC etc.)
• Solid experience in the development of video/image signal processing algorithms in C/C++
• Collaborative mindset, with solid written and verbal communication skills

Preferred Qualifications

• Experience in architecture design of video encoding and processing hardware accelerators
• Experience in FW algorithm and architecture for video codecs
• Experience in deep learning and neural-network based video processing algorithms and architecture
• Experience with SystemC modeling and reference model development