Job Details:

Job Description:

The Role and Impact

As a Mixed Signal Design Verification Engineer in the Power Solutions and Sensors team, you will play a pivotal role in ensuring the functionality and performance of mixed signal logic components critical to Intel's success in delivering critical IPs on advanced process nodes. Leveraging your expertise in mixed signal verification, you will contribute to the development and validation of IPs that meet rigorous microarchitecture specifications, impacting the quality, reliability, and efficiency of Intel's technologies. Your contributions will directly support Intel's mission to drive innovation and deliver best-in-class solutions across its portfolio of products.

Key Responsibilities

• Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design specifications are met.
• Develop IP verification plans, test benches, and verification environments to ensure comprehensive coverage of mixed signal microarchitecture specifications.
• Execute detailed verification plans, define and run system simulation models, analyze power and timing, and uncover bugs to optimize design functionality.
• Debug issues in the presilicon environment through replication, root cause analysis, and implementation of corrective measures to resolve failing tests.
• Collaborate with digital and analog architects, RTL developers, and physical design teams to enhance the verification of complex architectural and microarchitectural features.
• Drive technical reviews of test plans and proofs with design and architecture teams, documenting all processes and findings.
• Maintain and continually improve functional verification infrastructure, methodologies, and tools to align with evolving industry standards.

Qualifications:

Minimum Qualifications

Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field.

• 4-12 years of relevant experience
• Proficiency in System Verilog, UVM, and Verilog for mixed signal verification.
• Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa.
• Strong scripting skills in Python, Perl, or Tcl for testbench automation.
• Knowledge of standard protocols including JTAG/IJTAG/CRI/APB, and multi-clock domain mixed signal designs.
• Expertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.

Preferred Qualifications

• Familiarity with Mixed Signal IP validation.
• Experience with low-power design techniques, such as UPF and clock gating.
• Knowledge of Formal Property Verification tools and version control systems like Git, Perforce, or CVS.
• Strong collaboration and communication skills, with the ability to work effectively within dynamic, multi-disciplinary teams.

Join us to shape the future of technology by driving verification excellence at Intel. Apply today and be a part of our journey to deliver world-class innovations.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.