Synopsys

Descriptions & Requirements

Job Description and Requirements

ASIC Digital Verification Lead

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned verification expert with 10-15 years of experience in the semiconductor domain, passionate about ensuring the highest quality in complex IP designs. You have a deep technical foundation in ASIC digital design and verification, complemented by advanced knowledge of UVM, SystemVerilog, and industry best practices. Your experience with high-speed serial link protocols such as USBx, PCIe, or SATA positions you as a subject matter authority, capable of addressing intricate technical challenges with confidence.

You thrive in dynamic, collaborative environments and are eager to mentor and inspire others. Your problem-solving mindset and commitment to excellence drive you to explore innovative solutions and continuous improvements. You are recognized for your ability to communicate complex ideas clearly across multidisciplinary teams and for leading by example. Adaptable and proactive, you embrace Agile methodologies and enjoy playing a pivotal role in project success—balancing technical leadership, process optimization, and hands-on verification expertise. Your dedication to quality, efficiency, and teamwork makes you an indispensable contributor in high-impact projects.

What You’ll Be Doing:

• • Have 10-15 years of relevant experience in design verification or related fields
  • Lead the verification of complex IP designs, including functional, coverage, and regression testing
  • Work collaboratively with architecture and design teams to achieve implementation goals
  • Create, review, and oversee test methodologies and execution, ensuring compliance with industry standards (e.g., UVM, SystemVerilog)
  • Build robust verification environments using constrained random stimulus, assertions, and coverage metrics; run and debug simulations for quality
  • Develop and execute detailed test plans, setting and achieving coverage targets
  • Apply Agile practices such as code reviews and sprint planning
  • Drive efficiency and process improvements in verification through new methods and tools
  • Provide technical leadership through mentorship, teamwork, and example
  • Communicate effectively with cross-functional teams and management
  • Work on functional verification of high-speed serial link PHY IPs for USBx, PCIe, SATA, or similar protocol standards
• Preferred Qualifications:
  • Deep expertise in verification methodologies (such as UVM, SystemVerilog)
  • Prior experience in high-speed serial links (SERDES, USB, PCIe, SATA)
  • Proven ability to work in Agile teams and deliver results
  • Excellent problem-solving, communication, and leadership skills

The Team You’ll Be A Part Of:

You’ll join a high-performing, inclusive team of engineers dedicated to delivering world-class IP cores for the semiconductor industry. The team collaborates across functions—including architecture, design, and verification—to solve complex challenges and push the boundaries of chip performance and reliability. We value open communication, continuous improvement, and the collective pursuit of excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.