Google

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
• Experience capturing design specification in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
• Experience working with one or more formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or Display and Video 360).

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Plan the formal verification strategy and create the properties and constraints for digital design blocks.
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
• Contribute improvements to methodologies to enhance formal verification results.
• Architect and implement reusable formal verification components.