eero is a market leader in mesh wifi systems, with the mission to make technology in our homes just work. eero's vision is to deliver the perfect internet experience for every home, every device, for everyone. We are intentional and empathetic when defining and solving customers' problems and needs. We ensure our product experience is comprehensible, straightforward, reliable, and secure.
As a lead HW validation engineer, you will be responsible for partnering with our JDM suppliers to deliver HW validation of the entire roadmap of eero products. This role requires the ability to intake requests, prioritize activities, provide leadership updates, and escalate to both eero and partner leadership. Building mechanisms will be critical in order for eero’s roadmap to scale. In this role you will need to build mechanisms to scale verification to handle a greater load of projects. You will work closely with the engineering organization to understand
the designs, to be close to the details, but will act as a checks and balances to the engineering design team. This role must be objective and comprehensive to build bullet proof test plans;
while also thinking big to build new test cases and prioritize effectively. This leader will rely
heavily on CM/JDM resources to execute test plans and will build mechanisms to inspect that
work was done correctly.
Key job responsibilities
Defining comprehensive unlicensed/licensed RF parametric HW characterization and validation to ensure wireless products performance.
Translating system level requirements to sub-system, module, component and chipset level requirements and vice-versa working with chipset vendors and system teams.
Leading debug efforts and driving cross-functional team discussions towards debug, root-cause and corrective action steps of issues.
Performing feasibility investigation on new technologies, RF requirements, RF features, test methodologies and RF components.
Working with system design engineers and CM team, tracking validation progress, presenting and bringing insight into data, and representing status in presentations to senior management.
Demonstrating the ability to prioritize tasks, manage HW validation schedules and milestones to fit into PDP gates, and have backbone to push back on schedule when needed the design is not ready.
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