Google

Minimum qualifications:

• Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
• 8 years of experience working with CPU/GPU benchmark characterization
• Experience with microarchitecture technology.

Preferred qualifications:

• Master's degree in Electrical, Mechanical Engineering, or equivalent practical experience.
• Experience with performance analysis tools.
• Knowledge of system software components, such as Linux, drivers, and runtime.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Collaborate with architecture and system design teams to define clear verification goals and objectives, with a focus on CPU-specific features and performance, particularly within the ARM architecture.
• Design and implement reusable DV infrastructure components, including testbenches, stimulus generators, and checkers, tailored for CPU verification within the ARM ecosystem. Create and enhance CPU testbench DV flow, focusing on compilation/linking, memory loads, debug hooks, and adherence to ARM specifications.
• Define and track key coverage metrics to ensure thorough verification and identify potential design flaws in CPU Sub-System.
• Contribute to power-aware verification, gate-level simulations, and post-silicon CPU bring-up.
• Work with AMBA buses like CHI (Coherent Hub Interface) and ACE (AXI Coherency Extensions), as well as cache coherency protocols.