Minimum qualifications:
- Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience.
- 5 years of experience with static timing analysis, synthesis, physical design & automation.
- Experience in physical design tool automation such as synthesis, P&R and sign-off tools.
Preferred qualifications:
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of RTL languages (e.g., Verilog and SystemVerilog).
- Knowledge of timing constraints, convergence and sign-off.
- Knowledge of STA, EMIR and PDV sign-off methodologies.
- Understanding of parasitic extraction tools and flow.
About the Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with Post-Si teams to improve and debug Vmin and yield related issues.
- Explore specific new custom circuit opportunities for optimized Power, Performance, and Area (PPA) for high-performance, low-power subsystems.
- Work with the testchip teams on latest process nodes to build, validate and characterize custom Intellectual Property (IPs).
- Schedule and plann for custom IP for product interception.
- Work on early prototyping of subsystems to deliver optimized PPA recipes.
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