Wipro

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Junior Design Verification Engineer

We are seeking a motivated Junior Design Verification Engineer to join our hardware team. You will assist in verifying digital designs through simulation, testbench development, and debugging. Working under senior engineers, you’ll help ensure design functionality, coverage, and compliance with specifications.

Responsibilities:

• Develop and maintain SystemVerilog/UVM-based testbenches
• Write and execute test cases for functional verification
• Debug RTL and simulation failures
• Support regression runs and coverage analysis
• Collaborate with design, DFT, and validation teams

Requirements:

• Bachelor’s degree in Electrical/Computer Engineering or related field
• Familiarity with Verilog/SystemVerilog
• Understanding of digital logic and basic verification concepts
• Strong problem-solving and communication skills

Must Have :

Familiarity with coding in C and Python languages

Strong understanding of digital design concepts (FSMs, pipelining, clock domains, etc.).

Good understanding of basic Computer Architecture - CPU, memory, peripherals,

address decoding, cache concepts etc.

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.

Good to Have :

• Experience with UVM (Universal Verification Methodology).
• Knowledge of EDA tools such as Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Questa.
• Understanding of SoC architecture, bus protocols (AXI, AHB, SPI, I2C), and memory systems.

Mandatory Skills: VLSI HVL Verification .

Experience: 1-3 Years .

Expected annual pay for this role ranges from $33,000 to $76,000 . Based on the position, the role is also eligible for Wipro’s standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.