Google

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
• 8 years of industry experience in embedded SRAM design (cell and macro) and characterization.
• Experience in CMOS technology and device characterization, process integration and SPICE simulation.
• Experience with investigative analysis and investigative tools such as JMP, spreadsheets.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.
• 10 years of industry experience in both Foundry and Fabless environment.
• Experience in product-level testing in Static Random Access Memory (SRAM) memory including yield and parametric evaluation.
• Excellent communication and collaboration skills to work effectively with cross-functional teams.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Work with foundry and IP team to analyze SRAM bitcell and macro designs in cutting edge nodes for optimal performance, power consumption, and minimal area for mobile applications.
• Conduct detailed bitcell and periphery simulation and analysis to evaluate performance, power, and area tradeoffs. Working with the RO/Power, Performance, Density, and Area (PDPPA) team to evaluate PPA accounting both logic and memory at IP level.
• Work with the IP and test team to develop and execute post-silicon validation to verify the functionality and performance of SRAM in the silicon environment. Identify and debug functional and performance issues in SRAM during post-silicon bring-up.
• Work with architecture, design, verification, test and FA teams to ensure successful SRAM integration and productization.
• Work with external and internal teams to explore novel embedded memory technologies to enhance mobile AI performance.