Conduct design and development of CMOS image sensor architectures; work on transistor level design of analog and mixed-signal circuits, which areused for CMOS Image Sensor, such as asic_pixel array, column, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso; work on whole chip floorplan design, block layout design and pad placement; collaborate with layout engineer on whole chip layout integration and suggest possible layout improvements using Cadence Virtuoso; perform block level and chip level simulation of image sensor readout circuit by simulators such as Analog FastSPICE (AFS), Empyrean ALPSand NanoSpice; perform layout verification such as DRC, LVS, PERC check by using Siemens Caliber; perform whole chip IR drop check by using Ansys Totem; conduct script modification using Perl programming language; collaborate with Digital Engineers to define and design the analog to digital interface; collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors; propose innovative and creative solutions along with new circuit R&D and be ahead of current technology.
Job Requirements:
Master’s degree in Electrical Engineering, Computer Engineering, or related fields; plus two (2) years of experience in chip layout
Must have the following skills/experience:
Annual base salary for this role in California, US is expected to be between $110,000 - $130,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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