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Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).
Preferred qualifications:
- PhD in Electrical Engineering or Computer Science.
- Experience leading front-end design for modern processor components or AI accelerators.
- Experience with SOC design, architect, and integration.
- Experience with ARM Instruction Set Architecture.
About the Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
- Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
- Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting Performance Power Area(PPA) goals with production quality.
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
- Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.
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