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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience with chip industry.
- 3 years of experience in machine learning or Tensor Processing Unit (TPU).
- Experience in cooperating with cross teams in chip design cycles from pre-silicon to post-silicon and workload analysis on the devices.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in one or more related areas in on-device machine learning, Dynamic and Voltage and Frequency Scaling (DVFS) governor, scheduler, performance and power analysis, Graphics Processing Unit (GPU), Central Processing Unit (CPU).
- Experience in automation programming (e.g., Python, Shell script etc.).
- Experience in model break-down, pin-point bottleneck, and comparison with different platforms.
- Experience in operator offloading implementation from Central Processing Unit (CPU) to Tensor Processing Unit (TPU) or Graphics Processing Unit (GPU).
About the Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Collaborate with cross-functional teams for performance, power analysis results in both qualitative and quantitative fashion, especially in the Machine learning (ML) area on Tensor Processing unit (TPU) including model architecture analysis, on-device benchmarking, and optimization.
- Study the behavior and characterization of a variety of workloads on devices to explore opportunities for Hardware/Software (HW/SW) co-optimization, in addition to end-to-end use case optimization.
- Participate in both evaluations of future ASIC architecture and software optimization.
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