Google

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 4 years of experience with physical design flow such as floor planning, place and route, or physical verification.
• Experience with low-power design techniques, such as power gating, clock gating, or voltage scaling.

Preferred qualifications:

• Experience in using Machine Learning (ML) in physical design.
• Knowledge of machine learning algorithms from logistic regression to deep neural networks and reinforcement learning.
• Knowledge of data structures and algorithms.

About the Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to improving Power Performance Area (PPA) using machine learning techniques. You will use the experience of physical design and machine learning to solve technical problems and improve on Power, Performance, Area and Schedule. You will work on design and optimizations, floorplan, place and route, clock and power planning, timing analysis, and Power Delivery Network (PDN) analysis. You will collaborate across Alphabet working with design, CAD and machine learning teams.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Deploy Artificial Intelligence (AI) solutions into chip design, work with internal teams, Google DeepMind and other teams to explore solutions and apply to improve chip design PPA or cycle time.