Synopsys

Descriptions & Requirements

Job Description and Requirements

SerDes Digital IP Team is seeking for a highly motivated and innovative digital verification engineer with knowledge of ASIC development flow. The candidate would be working as part of a particularly experienced digital IP design and verification team, targeting the current and next generation high speed SERDES, such as 224G Ethernet, Gpon, PCIe4.0, DP2.0, USB and MIPI MPHY products.

Solid theoretical and practical background in high-speed SERDES and data recovery circuits is a solid plus.

The position offers an excellent opportunity to work with a professional team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.

Key Qualifications

• BSEE with 8+ years or MSEE with 5+ years of relevant experience in the industry
• Good experience in ASIC RTL verification at both chip level and block level
• Must be familiar with Verilog language
• Good knowledge of System Verilog, UVM and Verification Methodology
• Good knowledge of VCS and DC/PT tool
• Theoretical and practical background in SerDes is a solid plus
• Knowledge of digital design and synthesis constraints and flows is a solid plus
• Scripting experience in Shell, Perl, Python and TCL is a plus
• Demonstrates good skills to analyze and solve problems
• Demonstrates good skills to communicate with both local and global team members

Preferred Experience

• Defining verification strategy and writing test plan with high quality
• Building complex testbench and writing test-cases in System Verilog
• Debugging failure and collecting coverage to fulfill feature verification requirement
• Interacting with Application Engineers for customer support

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.