Synopsys

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles:

• Senior ASIC Digital Design Engineer
• Lead ASIC Design Engineer
• RTL Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional in the field of ASIC digital design, with a passion for innovation and a drive to create cutting-edge technology solutions. You have extensive experience with protocols such as AMBA, DDR, PCIe, Ethernet, USB, and UFS. Your programming skills include System Verilog, TCL, Perl, or Python, and you have a knack for extracting detailed requirements from high-level specifications. You work independently, with precision, and have a strong desire to drive innovation in your field. Excellent communication skills are a given, allowing you to collaborate effectively with cross-functional teams.

What You’ll Be Doing:

• Understanding the requirements and architecting the subsystems based on these requirements
• Integrating the RTL and driving design tasks to complete the subsystem
• Signing off on front-end implementation flows such as synthesis timing closure using DC/Fusion Compiler, SpyGlass CDC/RDC checks, and low power architecture
• Leading verification closure by interacting with verification teams
• Driving the life-cycle of subsystems through various phases, from requirements to delivery
• Collaborating with design and verification teams to ensure smooth project execution

The Impact You Will Have:

• Enhancing the performance and capabilities of our Digital Interface IP Subsystems
• Reducing time-to-market for high-performance silicon chips
• Ensuring the reliability and efficiency of our subsystem solutions
• Contributing to the development of innovative technologies that shape the future
• Driving continuous improvement in design and verification processes
• Supporting our mission to power the Era of Smart Everything with advanced technology

What You’ll Need:

• Hands-on/lead experience with subsystems/SoC design, architecture, and implementation
• Proficiency in Verilog/System Verilog coding and simulation tools
• Experience with implementation flows such as synthesis flow, lint, CDC, and low power
• Strong understanding of one or more protocols: AMBA, DDR, PCIe, Ethernet, USB, UFS
• Programming skills in System Verilog, TCL, Perl, or Python

Who You Are:

• Independent and precise worker with a drive for innovation
• Excellent communicator with the ability to collaborate effectively with cross-functional teams
• Detail-oriented and capable of extracting detailed requirements from high-level specifications
• Proactive problem solver who takes ownership of projects

The Team You’ll Be A Part Of:

You will be a senior member of the Synopsys Solutions Group Subsystems team, which is developing high-performance Digital Interface IP Subsystem solutions for DDR, PCIe, Ethernet, UFS, USB, and other interface protocols. Based in our offices in Bangalore/Hyderabad, India, you'll be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.