Synopsys

Descriptions & Requirements

Job Description and Requirements

• Lead Formal Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced Senior Formal Verification Engineer with a strong track record in ensuring the robustness and quality of digital design hardware IPs. You have a deep understanding of formal verification methodologies and are proficient in using industry-standard tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal. You excel in developing and driving formal verification plans, identifying and implementing state-of-the-art methodologies, and mitigating verification risks early in the design phase. Your excellent problem-solving abilities and proactive approach enable you to address verification challenges effectively. You are a collaborative team player who thrives in a dynamic environment and enjoys mentoring junior engineers while leading high-performing teams to deliver best-in-class, verified IPs.

What You’ll Be Doing:

• Leading and mentoring a team of formal verification engineers to ensure high-quality IP delivery.
• Developing and driving formal verification plans, aligning with project timelines and IP deliverables.
• Defining test plans tailored to high-complexity digital IPs such as UFS MIPI Unipro I3C, AMBA, and other interconnect protocols.
• Identifying and implementing state-of-the-art formal verification methodologies and tools, including assertions, SystemVerilog Assertions (SVA), and custom verification environments.
• Driving innovation to enhance verification efficiency and coverage.
• Evaluating and mitigating verification risks early in the design phase to ensure IPs meet high-quality standards.

The Impact You Will Have:

• Ensuring the robustness and quality of our digital design hardware IPs.
• Delivering best-in-class, verified IPs to semiconductor design companies globally.
• Enhancing verification efficiency and coverage through innovative methodologies.
• Mitigating verification risks early in the design phase, ensuring timely and high-quality IP releases.
• Contributing to the development of high-performance silicon chips and software content.
• Driving continuous technological innovation in chip design and verification.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Advanced degrees preferred.
• 2 – 6 years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs.
• Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance.
• Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal.
• Extensive experience in digital design and verification for high-speed interconnect protocols.

Who You Are:

• An excellent problem solver with a proactive approach to identifying and addressing verification challenges.
• A collaborative team player who thrives in a dynamic environment.
• An effective communicator who can lead and mentor junior engineers.
• An innovative thinker who drives continuous improvement in verification methodologies.
• A detail-oriented professional committed to delivering high-quality IPs.

The Team You’ll Be A Part Of:

You will be part of a high-performing and engaged formal verification team dedicated to ensuring the robustness and quality of our digital design hardware IPs. Our team collaborates closely with cross-functional teams to deliver best-in-class, verified IPs to semiconductor design companies globally.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.