Experienced DFT Engineer with 12-16 years of industry experience in the VLSI domain to join our dynamic team. The ideal candidate will have a strong background in Design for Testability (DFT) methodologies and techniques, with a proven track record of successfully delivering high-quality DFT solutions for complex System-on-Chip (SoC) designs. The role requires hands-on experience in DFT architecture, implementation, and verification, along with excellent problem-solving skills and a collaborative mindset to work effectively within cross-functional teams.
Requirements
12-16 years of industry experience in DFT engineering, with a proven track record of delivering successful DFT solutions for complex SoC designs.
Proficiency in industry-standard DFT tools such as Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test.
Strong expertise in DFT architectures, methodologies, and techniques, including scan insertion, ATPG algorithms, BIST Architectures, and JTAG.
Experience with DFT verification methodologies and tools, including simulation-based and formal verification techniques, fault modeling and coverage analysis.
Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
Excellent problem-solving skills and attention to detail, with the ability to analyze complex DFT issues and implement effective solutions.
Strong communication and interpersonal skills, with the ability to collaborate effectively within cross-functional teams.
Proven leadership skills and experience in mentoring junior engineers and driving technical initiatives.