OMNIVISION

Description

Job responsibilities:

• Responsible for RTL design and verification using Verilog / HLS for ISP pipeline / IP Blocks
• Technical Lead RTL and Algorithm engineers for the best performance
• Optimize Design for Low Cost and Low Power consumption as considering Image Quality
• Reconstruct ISP pipeline for each product according to a requirement

Qualifications:

• Must have experience/knowledge in CMOS sensor or camera ISP system
• Must have 7+ year experience/knowledge in RTL design and verification using both HLS and Verilog
• Must have C/C++ programming skills
• Experience/knowledge in Algorithm of Image processing in Camera
• Result oriented and embraced change behaviors
• People management skill / experience or Project management skill is a plus
• PhD / MS / BS in Electrical Engineering, or Computer Science and Engineering, or related field, or equivalent work experience
• Business level Japanese & English communication skill