Description
- Responsible for RTL design and verification using Verilog and System Verilog
- Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation
- Work closely with Analog Design Engineers to develop Sensor Timing Control logic
- Implement Image Signal Processing blocks into System
- Optimize Design for Low Power consumption
- Work on Physical Design (Synthesis, Formal Verification, STA, DFT)
- Silicon bring-up and production support
- 7+ years experience with RTL design and verification
- Experience as a Technical Leader to develop Digital System on silicon
- Good communication and interpersonal skills
- Experience / knowledge in CMOS Image Sensor and/or Image Signal Processing is a plus
- Experience / knowledge in mixed-signal design is a plus
・Result oriented and embraced change behaviors
・People management skill / experience or Project management skill is a plus
- BS in Electrical Engineering, or Computer Science and Engineering, or related field, or equivalent work experience
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