Samsung

Position Summary

1. Secure an optimal digital IP and circuit by understanding required functions to be developed and designing and verifying them in line with the required goals.

Role and Responsibilities

Job Profile – RTL Micro-architecture Design Engineer (SOC Integration)

2 to 15 years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU/GPU Subsystem or other Mobile SoC Subsystem.

• Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.
• Creating micro-architecture and detailed design documents for SoC Subsystem design keeping in mind performance, power, area requirements.
• Strong debugging skills and very good experience in DV tools like Verdi, NCSIM.
• SOC Integration experience preferred of Top Level, Block Level or Subsystem level.
• Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team.
• Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis.
• Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must.
• Understanding and defining constraints and critical high speed path timing closure working with back end teams

Job Profile – RTL Micro-architecture Design Engineer (GPU)

• Design and Engage with other architects within the IP level to drive the Micro-Architectural definition
• Deliver quality micro-architectural level documentation
• Produce quality RTL on schedule meeting PPA goals.
• Work within the GPU/CPU team to drive power reduction including estimation, analysis, and optimization, flow setup, and methodology improvements.
• Collaborate with system architects and designers, define use cases, identify and prototype power and perf-per-watt optimizations.
• Run performance models and power tools, write scripts, analyze data, and evaluate tradeoffs against project goals.
• Job Profile – RTL Micro-architecture Design Engineer (IP Design)
• Design and Engage with other architects within the IP level to drive the Micro-Architectural definition
• Deliver quality micro-architectural level documentation
• Produce quality RTL on schedule meeting PPA goals.
• Drive power reduction including estimation, analysis, and optimization, flow setup, and methodology improvements.
• Collaborate with system architects and designers, define use cases, identify bandwidth requirements and performance targets
• Multimedia knowledge related to Image Processing and Display architectures is needed for senior candidates
• Sound understanding of ASIC Design flow
• Working knowledge of C/C++ is added advantage
• Working knowledge of Linux and basic scripting
• Tools : Spyglass, Synopsys DC, Meridian CDC, Cadence/Synopsys/Mentor simulators
• Languages : Verilog HDL, System Verilog, C/C++

Skills and Qualifications

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