Job Description
In this role, you will work with software and hardware engineering groups to define the next-generation hih performance Data Center SOC
Requirement of the Job
- Work with IO architecture team to design the IO subsystem of datacenter SOC
- Integrate, Configure, Debug IO IPs and build SOC subsystem
- Write RTL of critical IO functional blocks
- Work with DV and emulation team to bring up IO subsystem
Job requirements
BS/MS/Ph.D. in Electronics Engineering with minimum of 5 years of chip design experiences.
- Good understanding of PCIe protocol and architecture
- Hands-on experience of the design and integration of PCIe Controller and PHY
- Hands-on experience in SOC integration
- Experience of debugging sophisticated system such as PCIe RC and Endpoint
