Marvell Technology

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Custom Compute & Storage (CCS) Business Unit, is one of Marvell's fastest growing business units. In CCS, we focus on helping our customers with their custom designs for cloud-based AI applications as well as customers in the enterprise and carrier markets.

What You Can Expect

• Develop and execute verification plans for reset and clocking blocks.
• Create and maintain testbenches and test cases related to reset and clocks.
• Lead a team of verification engineers working on and supporting reset/clock infrastructure.
• Perform functional and performance verification.
• Debug and resolve design and verification issues.
• Collaborate with design and architecture teams to ensure verification coverage.

Other Skills:

• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.
• Ability to mentor junior engineers and lead verification projects.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 20+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-15 years of experience.
• Proficiency in SystemVerilog and UVM.
• Significant experience in verifying reset and clocking blocks for large designs 5nm and below.
• Experience in leading a team of verification engineers.
• Experience in developing and supporting global verification infrastructure (RST/CLK).
• Proficiency with simulation tools (e.g., VCS).
• Knowledge of scripting languages (Python, Perl, TCL).
• Strong knowledge on chip architecture/RTL/verification

Expected Base Pay Range (USD)

189,800 - 280,830, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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