Introduction
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Your role and responsibilities
We are offering an Master-Thesis: Simulation-based SRAMs and Regfiles Usage Measurement for Precise Soft Error Rate (SER) Derating
High-performance processors use both flip-flops (latches) in the functional logic and arrays such as SRAMs and register-files as storage elements. The proportion of arrays is many times greater than that of latches. Due to the higher density, the cells of these arrays are also more sensitive to cosmic radiation and are more vulnerable to soft errors. Soft errors usually do not destroy SRAM transistor structures but can flip single (SEU) or multiple data bits (MBU). SEU and MBU can be recovered/overwritten/masked. If they’re propagated and undetected, they can cause data-integrity (DI) issues. Therefore, a major part of soft errors hits array structures. Array structures (SRAM, register-files) require special error detection and correction design effort. The optimal protection can be determined with calculation of fail probability based on physical implementation data (e.g., cell dimensions, failure in time rate, array size, etc).
An important parameter for array failure probability due to cosmic particles is the ‘hold time’ for stored data, the write/read frequency, etc. This ‘exposure’ parameter is key for precise reliability assessment of processor arrays, and it is assessed only roughly by logic designers (array customer) as a general assessment. SEU and MBU probability increase with longer hold time of stored data and decreases with increasing array refresh/rewrite rate. Pre-silicon prediction of DI-probability is key for the selection of appropriate protection for arrays (SRAM, regfiles). That requires precise array vulnerability data / parameter.
We developed a new method including special VHDL attributes (SER attributes) and virtual counter structures to enable monitoring and measuring of precise values of array data residency or array usage-parameters in an AWAN simulation model. An AWAN model represents an exact RTL description and can execute cycle-based the same workload as the real hardware.
This master thesis uses an existing simulation environment to run a current processor AWAN model including the mentioned (‘compiled-in’) SER attributes and counter structures in a provided real workload scenario and to perform the required measurements for data residency in a post-process.
Self-developed innovative ideas can be incorporated, as well as a graphical evaluation using histograms for array utilization. An existing environment (for processor A) should be implemented and enabled in an actual processor (processor B) simulation environment. Simulation-experiments with available testcases / workloads (for processor B) should be carried out to collect measurement data. Evaluation scripts were developed in the existing environment (processor A). These post-process scripts will be implemented in the current environment (processor B) and possibly adapted and improved. The evaluation (processor B data) will be carried out in consultation with experts. Comprehensive documentation and instructions for setting up and running the newly implemented environment (processor B environment) must be prepared. Experimental results (processor B) should be graphically generated and evaluated using histograms (following the example of processor A). Your own innovative ideas for evaluation can be incorporated.
Thankfully, you’re not alone: we are a friendly and international team that knows not only how to use tools, but also how to develop them. We are here to help you out when you’re stuck, to discuss your findings, and to celebrate your success.
If you’re interested please get in contact with us and include in your response all relevant documents (preferably all in one single pdf file):
1. Cover Letter incl. your availability (earliest start and latest end date)
2. CV incl. your level of German
3. Certificate of enrollment from you university
4. Current transcript of records and other relevant certificates / references
5. Non-EU citizen studying in Germany: copy of passport, residence and work permit
6. Non-EU citizen studying elsewhere: prove of identity incl. place of birth
We are looking forward to your application!
Required education
Bachelor's Degree
Required technical and professional expertise
Study of computer science, electrical engineering or a similar direction
Programming skills (e.g. Python, C++)
Knowledge of Development tools / technologies (e.g. git, )
Strong abilities in communication in English
Preferred technical and professional experience
Interest in chip design and verification
Experience in software profiling methodologies and tools
Processor Architecture, Instruction Set Architecture principle
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