Job Description and Requirements
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
Get to know more about Synopsys Foundation IP: Logic Library, Memory Compiler, OTP, NVM | Foundation IP | Synopsys
You are an experienced Memory Layout Design Engineer with a passion for developing cutting-edge technology. You possess a Bachelor’s or Master’s degree in Electronics Engineering, Telecommunication, Physics, or related fields. With a minimum of 2 years of experience in layout design, you have advanced knowledge of Custom Layout and a deep understanding of Embedded Memory Layout. Your strong communication, documentation, and analytical skills enable you to collaborate effectively with cross-functional teams. You are detail-oriented, proactive, and thrive in a dynamic environment where innovation and continuous improvement are paramount.
You will be part of a dynamic and innovative team focused on developing high-performance silicon IPs. Our team collaborates closely with design engineers, verification engineers, and other stakeholders to deliver best-in-class solutions. We are committed to continuous learning and improvement, fostering an environment where creativity and technical excellence thrive.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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