Microchip’s Wireless Solutions Group is seeking a frontend chip implementation engineer to support SOC development for our next generation, mixed signal, wireless products. The role will include the areas of RTL synthesis, DFT implementation, STA using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.
• Frontend implementation engineer for the WSG Bluetooth Silicon Development team in Taiwan
• In charge of RTL-to-Netlist Synthesis and Timing Budgeting/Closure
• DFT/SCAN/MBIST insertion and ATPG, SCAN/MBIST pattern verification and debugging
• Implement low power flow with UPF
• Responsible for RTL-to-GDS flow methodology research and development
• Familiar with Synthesis/Formal/STA flow;
• Familiar with DFT/ATPG/MBIST flow ;
• Familiar with UPF flow ;
• Familiar with Linux environment and Tcl/Perl/Python/Shell script ;
• Familiar with verilog simulation and debugging ;
• Good communication and team work skills ;
• Requires a strong understanding of digital implementation tools and flow.
• Work closely with our digital design and physical design team to effectively collaborate on chip implementation activities.
• Requires prior working experience with the following tools: Design Compiler, PrimeTime, DFT Compiler, Tessent Scan/MBIST, Formaility, SpyGlass, Verdi
• Experience with advance technology node (65nm and below) is a plus
• Experience with advance DFT techniques (at-speed-test / compression scan) is a plus.
• Experience with backend physical design is a plus.
• Experience with ARM or MIPS core implementation is a plus.