Senior Engineer II


Job Description


  • As part of the MCU32 verification group, the successful candidate will be a responsible for SOC Level/IP Level verification activities.
  • The candidate will interact regularly with the cross site team to achieve these goals.
  • Responsible for preparing Verification plan, Requirements document at Module and Chip level.
  • Responsible for developing Verification environment using SV(System Verilog).
  • Responsible for developing random and directed test-suite.
  • Develop System Verilog assertions/cover point.

Job Requirements


  • 5-8 years of industry work experience.
  • Languages (Must) : Verilog and Systemverilog.
  • Methodologies (Any one) : OVM, VMM., UVM.
  • EDA Tools(One of them is must): Questasim, VCS, NCSim, NCVerilog.
  • Good understanding of digital design fundamentals.
  • Proficient with Unix environment and common scripting languages.
  • Expertise in Testplan development. 
  • Expertise in Functional / Code Coverage activity.
  • Experience in SOC/IP level verification activities.
  • Testbench development in Verilog/SystemVerilog using verification methodology
  • Experience in using and integrating 3rd Party Verification IP’s.
  • Test case creation and regression suite development.
  • Experience of working on mixed Verilog/SystemVerilog and C/C++ environments
  • Experience of developing SOC level monitors / drivers / handshake blocks
  • Strong in simulation and debugging skills.
  • Experience in gate level simulation and debugging.
  • Good Knowledge of SOC peripherals like ADC/Timers/ECAN/USB/SPI/I2C.
  • Knowledge of revision control tools like CVS.
  • Should be able to handle tasks independently.
  • Good communication skills and the ability to work in a team environment. 
  • Experience with processor based verification.
  • Experience in UVM methodology.

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Confirmed 18 hours ago. Posted 30+ days ago.

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