· BS degree with 2~3+ years of applicable experience, MS degree with 1~2+ years of applicable experience in electrical engineering, microelectronics.
· Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
· Solid knowledge on LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM.
· Successful track records of taping out complex, 65/40/28 nm SOC chips.
· Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
· Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.