Lead Designer, 5G Radio ASIC Design

Nokia

Description

Nokia is a global leader in the technologies that connect people and things. With state-of-the-art software, hardware and services for any type of network, Nokia is uniquely positioned to help communication service providers, governments, and large enterprises deliver on the promise of 5G, the Cloud and the Internet of Things. 
Serving customers in over 100 countries, our research scientists and engineers continue to invent and accelerate new technologies that will increasingly transform the way people and things communicate and connect.
 

Team description

Nokia Mobile Networks (MN) is responsible for managing Nokia’s infrastructure assets and making select investments in advanced research and development to drive innovation for 5G applications. The Architectures, Technologies, and R&D Foundation (ATF) division within Mobile Networks creates valuable IP for Nokia by engaging with leading business-to-business (B2B) customers to enhance their competitive advantage.

ATF’s 5G DFE & RFIC program, located in Sunnyvale, California, innovates and develops differentiating wireless infrastructure solutions for Nokia’s 5G products.  The team is multi-disciplinary and enjoys fruitful collaborative partnerships with top universities, international research institutes and network operators. Be part of this exciting team and successfully drive the future of wireless communications!

We are now looking for Lead Designer, 5G Radio ASIC Design to join our team.

Qualifications

Key responsibilities 

In this role, you will be responsible for designing innovative low power digital blocks for 5G RFIC chip. The chip is warranted to address the proliferation of 5G, to be supported by cost-effective hardware. As a member of the 5G RFIC/DFE team, you will be an active contributor to team goals and, therefore, have a proven track record of professionalism.

 

Requirements 

In order to succeed in this exciting role, we expect you to meet one or more of following technical requirements:

• 6-8 years of ASIC digital design experience

• Experienced the full cycle production level ASIC design and tape out

• Proven track record of Verilog RTL coding experience is a must

• Experience in any of the following areas:

  •   High speed SerDes
  •   JESD204A/B     
  •   Digital FIR filter RTL implementation
  •   Formal verification
  •   Low power design concept, UPF implementation
  •   Chip level or block level Verilog simulation, knowledge of system Verilog or UVM
  •   Scripting skills in Tcl, perl

• Working experience of defining micro architecture from system specification

• Some exposures to the back-end related process, e.g. synthesis, timing analysis

• Good understanding the impact of timing on RTL design

• Strong communication and inter-personal skills, developing/driving concepts and ideas with other team members and across other parts of a large organization (or other companies). 

• MS in Electrical Engineering (or related discipline) desired.

Job

fNokia System on Chip Development

Primary Location

Europe North-Finland-Finland-Espoo

Schedule

Full-time

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Confirmed 12 hours ago. Posted 30+ days ago.

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