- Job Number: 31781442
- Austin, Texas, United States
- Posted: Jan. 25, 2017
- Weekly Hours: 40.00
In this role you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.
- The ideal candidate will have 3 plus years of hands on experience in STA
- Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies
- Timing Margin Fundamentals from synthesis to signoff
- Needs to be proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others
- Familiar with circuit modeling, including SPICE models and worst-case corner selection.
- Programming with Perl, TCL
- Timing Flow using industry standard tools.
- Experience with STA on large, complex designs and Multi-Scenario Timing Closure
- Familiarity with ECO techniques and implementation
- Good communicator who can accurately describe issues and follow them through to completion
•Working with design teams to understand and debug constraints, facilitate logic changes to improve timing
•Working with Physical Design and Logic Design teams, highlighting issues and best practices
•Help create timing ECO’s for project tapeout
•Create/maintain scripts and methodologies for analysis and runs
•Create documentation and help with guidelines/specs
•Deep analysis of timing paths to identify key issues
•Implement timing infrastructure
MSEE or equivalent is required.