Physical Design Engineer - Timing Job Number: 31785816Santa Clara Valley, California, United StatesPosted: Apr. 29, 2015Weekly Hours: 40.00Job SummaryIn this role you will be responsible for all aspects of timing, including working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.Key QualificationsThe ideal candidate will have 3+ years of hands-on experience in STA. Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies.Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.Familiar with circuit modeling, including SPICE models and worst-case corner selection.Strong programming skills with Perl, TCL.Experience with large design STA and Timing Closure.Familiarity with ECO techniques and implementationGood communicator who can accurately describe issues and follow them through to completionDescriptionCore Responsibilities: Working with design teams to understand and debug constraints, facilitate logic changes to improve timing. Working with Physical Design team, highlighting issues and best practices. Help create timing ECO’s for project tapeout. Create/maintain scripts and methodologies for analysis and runs. Create documentation and help with guidelines/specs. Deep analysis of timing paths to identify key issues. Implement timing infrastructure. EducationMSEE or equivalent is required.