The GPU Memory Hierarchy Design Verification Engineer will be responsible for the pre-silicon RTL verification of cache hierarchy and related units in a low power GPU design. This includes deep understanding of the micro-architectural details of these units, interactions between the units, and the connection of the uarch to the larger architectural intent of the GPU. A strong computer architecture background, experience in cache and memory subsystem verification, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence..
•Develop verification plans in coordination with design leads and architects •Create and maintain verification test bench components and environments •Generate directed and constrained random tests •Run simulations and debug design and environment issues •Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes •Create automated verification flows for block verification •Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs •Work with other block and core level engineers to ensure seamless verification flow
•BS/MS CE or EE