GPU Memory Hierarchy Design Verification Engineer


Company Type
  • Job Number: 39794431
  • Austin, Texas, United States
  • Posted: Jan. 6, 2017
  • Weekly Hours: 40.00

Job Summary

The GPU Memory Hierarchy Design Verification Engineer will be responsible for the pre-silicon RTL verification of cache hierarchy and related units in a low power GPU design. This includes deep understanding of the micro-architectural details of these units, interactions between the units, and the connection of the uarch to the larger architectural intent of the GPU. A strong computer architecture background, experience in cache and memory subsystem verification, and a solid foundation in verification methodology will be leveraged to close testing coverage with high confidence..

Key Qualifications

  • The ideal candidate will have relevant 3 plus years of experience including:
  • Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus
  • Strength in creating software solutions utilizing object oriented programming concepts
  • Expertise with HDL simulators and waveform viewers
  • Experience defining coverage space, writing coverage model, analyzing results
  • Experience working under strict schedule deadlines with the ability to manage multiple priorities
  • Strong knowledge of computer architecture, general purpose microprocessor
  • Experience and expertise in memory/cache sub-system micro-architecture, which could include L1, L2, L3 caches, coherent interconnects, MMUs or related blocks
  • Experience with Perl, Shell scripting, Makefiles, TCL a plus
  • Excellent communication skills and ability to collaborate
  • GPU experience, especially in the memory hierarchy area, is a plus


•Develop verification plans in coordination with design leads and architects •Create and maintain verification test bench components and environments •Generate directed and constrained random tests •Run simulations and debug design and environment issues •Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes •Create automated verification flows for block verification •Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs •Work with other block and core level engineers to ensure seamless verification flow



Read Full DescriptionHide Full Description
Confirmed 30+ days ago. Posted 30+ days ago.

Discover Similar Jobs

Suggested Articles

One Step Register
Need an account? Sign Up